Dual mode regulators are known that use a linear regulator mode for low currents and a PWM mode for medium and high currents. A PWM regulator switches a power transistor on and off at a regulated duty cycle to maintain a constant voltage at the output of the regulator. The high conductivity of the switching transistor results in low losses across the transistor. This makes the PWM regulator mode efficient for medium to high load currents. At very low currents, although there is low loss across the switching transistor, the losses from turning the transistor on and off at the high switching frequency (typically exceeding 1 MHz) become a significant factor in the regulator's efficiency.
At low currents, a linear regulator, also referred to as a low drop out (LDO) regulator, is more efficient than a PWM regulator because there are no switching losses, and the loss through the series transistor is not very significant at low currents.
In a dual mode regulator, when the load is put into a low current standby mode, for example, the regulator receives a signal initiating the transition between the PWM and LDO regulator modes, and the regulator rapidly changes modes by enabling and disabling the appropriate circuitry. Such a transition causes voltage spikes to appear at the regulator's output unless a large output capacitor is used. Applicants have discovered that the reasons for the voltage glitches include: 1) a poorly controlled handover of the voltage regulation control while one mode is being disabled and the other mode is being enabled; 2) a normally slow reaction time of the LDO regulator and very little current handling capability to handle glitches during the changeover.